This invention relates to chipset technologies generally and particularly to efficient memory management techniques.
As the speed of processors steadily increases, an efficient mechanism to access memory subsystems is becoming ever more significant in an overall system design.
Traditionally, a system controller is employed to exchange data between the system bus and the memory subsystem or between the various Input/Output (hereinafter I/O) devices and the memory subsystem in a system. Often times, the memory subsystem comprises Dynamic Random Access Memories (DRAMs), and the system controller usually includes one or more command queues to buffer the incoming memory commands issued by the processor(s) or I/O devices. Additionally, the system controller typically has read and write buffers to temporarily store data read from or written to the memory subsystem.
The write data buffers in the system controller reduce read response time, thereby improving system performance. For example, they can improve read response time by allowing read operations to be serviced immediately rather than waiting for all write operations to be committed to memory. Also, they can improve memory efficiency by amortizing bubbles present either on memory buses or at the core of memory due to write-read and read-write transitions.
Although the previously mentioned write buffers tend to improve the efficiency of memory, they are of finite size. As a result, their contents must be periodically drained to memory. Two approaches are commonly employed for draining write operations: 1) a high priority panic flush mechanism, which takes place when the buffers exceed a certain utilization threshold; and 2) a low priority flush mechanism, which occurs when the system goes idle. The high priority mechanism is demand driven and is a result of having write buffers with finite sizes. The low priority mechanism, on the other hand, is opportunistic. It attempts to drain write operations at opportune times to avoid interfering with read requests. It should be noted that the low priority flush may adversely impact the timing of subsequent requests for high priority activities, such as read requests, if the flush fails to complete before the high priority requests are presented to the memory subsystem.
In one embodiment, a method and apparatus for servicing a request for an opportunistic operation to a memory subsystem includes an enabling signal that is generated to service the request for the opportunistic operation according to any combination of the following information: availability of resources of the memory subsystem, status of pending requests for a high priority operation, and status of the request for the opportunistic operation.